The present invention relates, in general, to testing of semiconductor devices, and more particularly, to a modular self-test for embedded SRAMs which can be varied for a variety of SRAM architectures and sizes.
The acceptance of compiler developed integrated circuits, often referred to as application specific integrated circuits (ASICs) or standard cells, developed an increased need for improved test techniques for the large variety of circuits produced by those methods. Improved semiconductor manufacturing procedures provided increased complexity semiconductor devices, while compiler design techniques provided a means to rapidly develop designs of many different semiconductor devices. The resulting proliferation of complex ASIC semiconductor devices, increased the need for test methods that were flexible and that could be compiled concurrently with an ASIC design. One technique, generally referred to as self-test, placed circuitry on the ASIC device to accomplish testing of the ASIC device. Self-testing became increasingly important as ASIC devices included blocks of static random access memory (SRAM) that were embedded on the ASIC device. Previous self-test methods for embedded SRAMs were specifically designed for a particular type of memory cell and a particular memory configuration. Consequently, they were not variable and could not be compiled for testing various memory configurations. Since tests performed by those self-test circuits were generally limited to a particular memory cell configuration, they were not useful in determining failures of other types of cells. Addressing and data structures of those previous circuits were generally limited to a specific size of memory and a specific word width for the memory. Previous self-test methods often used serial access methods to provide addresses and data to an SRAM, and to read data back from the SRAM. Serial access limited the speed at which tests could access the SRAM and reduced the test's effectiveness in detecting noise induced coupling faults. Serial access self-test circuits were most effective for small memories (generally less than 2,000 total bits in the memory). Previous fault detection techniques were generally limited to known types of faults for the particular memory configuration used in the ASIC device, and were not sufficiently general to test a variety of memory sizes and memory cell structures. Most previous self-test circuits utilized one circuit and test method to determine memory faults and different ones to determine data retention errors. This approach increased the complexity of circuitry required to perform the tests. One result was that more time was required to generate memory addresses for a test than was required to read and test a location. Testing was slowed while the circuitry generated addresses, thereby reducing the test's effectiveness and increasing test time and costs.
Accordingly, it would be desirable to have a self-test circuit that is variable to test different SRAM memory sizes and memory cell implementations, that develops addresses and data in a parallel format which tests the memory's operating speed, that provides fault coverage which is suitable for a variety of memory sizes and configurations, that has a test sequence suitable for detecting faults in a variety of memory sizes and memory cell configurations, and that is independent of time required to develop addresses within the SRAM.